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S3C7565/P7565
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3C7565/P7565 single-chip CMOS microcontroller is designed for high performance in the application for Caller-ID, Telephone using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangable Microcontrollers). Featuring a DTMF generator, up-to-960-dot LCD direct drive capability, one 8-bit timer/counter and flexible two 8-bit timer/counters, and serial I/O interface, the S3C7565/P7565 offer an excellent design solution for a wide variety of applications requiring DTMF, LCD support. Up to 43 (including COM/SEG) pins in the 100-pin QFP package can be dedicated to I/O. Nine vectored interrupts provide a fast response to internal and external events. In addition the advanced CMOS technology a of the S3C7565/P7565 ensures low power consumption with a wide operating voltage range.
OTP
The S3C7565 microcontroller is also available in OTP (One Time Programmable) version, S3P7565. S3P7565 microcontroller has an on-chip 16 K-byte one-time-programmable EPROM instead of masked ROM. The S3P7565 is comparable to S3C7565, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7565/P7565
FEATURES SUMMARY
Memory * * 16K x 8-bit ROM 5,120 x 4-bit RAM (excluding LCD RAM) 8-bit Serial I/O Interface * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable
I/O Pins * * Input only: 4pins (Not including COM/SEG) 6pins (Including COM/SEG) I/O: 15pins (Not including COM/SEG) 43pins (Including COM/SEG)
LCD Controller/Driver * * * * * 60 SEG x 16 COM terminals 8, 12 and 16 com selectable COM 8-15: shared with port SEG40-59: shared with port Two kinds of LCD bias resistor value
Memory-Mapped I/O Structure * Data memory bank 15
Bit Sequential Carrier * Supports 16-bit serial data transfer in arbitrary format
8-bit Basic Timer * * Four interval timer functions Watchdog timer
Interrupts * * * Four external interrupt vectors Five internal interrupt vectors Two quasi-interrupts
8-bit Timer/Counter * * * * Programmable 8-bit timer External event counter Arbitrary clock frequency output External clock signal divider
Power-Down Modes * * * Idle mode (only CPU clock stops) Stop mode (main system oscillation stops) Subsystem clock stop mode
16-Bit Timer/Counter * * * * * * Programmable 16-bit timer External event counter Arbitrary clock frequency output External clock signal divider Configurable as two 8-bit Timers Serial I/O interface clock generator
Oscillation Sources * * * RC, Crystal or Ceramic for system clock Oscillation frequency: 0.4-6.0 MHz CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times * * * 1.12, 2.23, 17.88 s at 3.58 MHz 0.67, 1.33, 10.7 s at 6.0 MHz 122 s at 32.768 kHz (subsystem) - 40 C to 85 C
Watch Timer * * Time interval generation: 0.5 s, 3.9 ms at 32.768 kHz 4 frequency outputs to BUZ pin (0.5, 1, 2, 4 kHz) at 32.768 kHz
Operating Temperature *
Comparator * * 4-channel mode: Internal reference (4-bit resolution); 16-step variable reference voltage 3-channel mode: External reference
Operating Voltage Range * * * 1.8 V to 5.5 V (except DTMF and Comparator) 2 V to 5.5 V (include DTMF) 4.0 V to 5.5 V (include Comparator)
DTMF Generator * 16 dual-tone for tone dialing
Package Type * 100-pin QFP (1420C)
1-2
S3C7565/P7565
PRODUCT OVERVIEW
BLOCK DIAGRAM
P7.0/SEG55/CIN0 P7.1/SEG54/CIN1 P7.2/SEG53/CIN2 P7.3/SEG52/CIN3 P1.0-P1.3/ INT0-INT4 P2.0/CLO P2.1/VLC1 P2.2 P3.0/TCLO0 P3.1/TCLO1 P3.2/TCL0 P3.3/TCL1 P4.0-P4.3/ COM8-COM11 P5.0-P5.3/ COM12-COM15 P6.0-P6.3 SEG59-SEG56/ KS4-KS7 P7.0/SEG55/CIN0 P7.1/SEG54/CIN1 P7.2/SEG53/CIN2 P7.3/SEG52/CIN3 P8.0/SEG51/LCDCK P8.1/SEG50/LCDSY P8.2/SEG49 P8.3/SEG48 P9.0-P9.3/ SEG47-SEG44 P10.0-P10.3/ SEG43-SEG40
Comparator XIN RESET Input Port 1 XOUT XTIN XTOUT
Basic Timer
Watchdog Timer
Watch Timer Interrupt Control Block Instruction Register LCD Driver/ Controller Program Counter
VLC1 COM0-COM7 P4.0-P5.3/ COM8-COM15 SEG0-SEG39 P10.3-P6.0/ SEG40-SEG59
I/O Port 2
Clock
I/O Port 3 Internal Interrupts
I/O Port 4 I/O Port 5
Instruction Dcoder I/O Port 6 I/O Port 7 Arithmetic and Logic Unit
Serial I/O Program Status Word I/O Port 0 Stack Pointer
P0.0/SCK/KO P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 DTMF
DTMF Generator
I/O Port 8 I/O Port 9 8-Bit Timer/ Counter 16-Bit Timer/Counter (Two 8Bit Timer/Counter) 5K x 4-bit RAM
I/O Port 10
16KB ROM
Figure 1-1. S3C7565 Block Diagram
1-3
PRODUCT OVERVIEW
S3C7565/P7565
PIN ASSIGNMENTS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 DTMF P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/CLO P2.1/VLC1 P2.2 P3.0/TCLO0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P10.3/SEG40 P10.2/SEG41 P10.1/SEG42 P10.0/SEG43 P9.3/SEG44 P9.2/SEG45 P9.1/SEG46 P9.0/SEG47 P8.3/SEG48 P8.2/SEG49 P8.1/SEG50/LCDSY P8.0/SEG51/LCDCK P7.3/SEG52/CIN3 P7.2/SEG53/CIN2 P7.1/SEG54/CIN1 P7.0/SEG55/CIN0 P6.3/SEG56/K7 P6.2/SEG57/K6 P6.1/SEG58/K5
Figure 1-2. S3C7565 Pin Assignments (100-QFP Package)
S3C7565 (100-QFP-1420C)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P6.0/SEG59/K4 P5.3/COM15 P5.2/COM14 P5.1/COM13 P5.0/COM12 P4.3/COM11 P4.2/COM10 P4.1/COM9 P4.0/COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 P3.3/TCL1 P3.2/TCL0 P3.1/TCLO1
1-4
S3C7565/P7565
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7565 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Individual pins are software configurable as input or output. Individual pins are software configurable as open-drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-bit input port. 1-bit and 4-bit read and test is possible. 4-bit pull-up resistors are software assignable. Same as port 0 except that port 2 is a 3-bit I/O port. Share Pin SCK/K0 SO/K1 SI/K2 BUZ/K3
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P3.0 P3.1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
I
INT0 INT1 INT2 INT4 CLO VLC1 TCLO0 TCLO1 TCL0 TCL1 COM8-COM11 COM12-COM15
I/O
I/O
Same as port 0.
I/O
4-bit I/O ports. 1-, 4-bit or 8-bit read/write and test is possible. Individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as P4, P5.
P6.0-P6.3
I/O
SEG59- SEG56/K4-K7 SEG55/CIN0- SEG52/CIN3
P7.0-P7.3 P8.0-P8.1 I/O Input ports. 1, 4-bit or 8-bit read and test is possible. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. These pins can not be used as push-pull output. Refer to the NOTES of table 10-3. Port Mode Group Flags. Same as P4, P5.
SEG51/LCDCK SEG50/LCDSY
P8.2-P8.3
I/O
SEG49 SEG48 SEG47-SEG44
P9.0-P9.3 P10.0-P10.3 SCK SO I/O I/O I/O Same as P4, P5. Serial I/O interface clock signal. Serial data output.
SEG43-SEG40 P0.0/K0 P0.1/K1
1-5
PRODUCT OVERVIEW
S3C7565/P7565
Table 1-1. S3C7565 Pin Descriptions (Continued) Pin Name SI BUZ INT0, INT1 INT2 INT4 CLO TCLO0 TCLO1 TCL0 TCL1 CIN0 CIN1 CIN2 CIN3 DTMF LCDCK LCDSY COM0-COM7 COM8-COM11 COM12-COM15 SEG0-SEG39 SEG40-SEG59 K0-K3 K4-K7 VDD VSS RESET VLC1 XIN, XOUT XTIN, XTOUT TEST - - I - - - I Main power supply. Ground. Reset signal. LCD power supply. Crystal, Ceramic or RC oscillator pins for system clock. Crystal oscillator pins for subsystem clock. Chip test input pin. Hold GND when the device is operating. P2.1 - - - O I/O I/O External interrupt (triggering edge is selectable) LCD segment signal output. Pin Type I/O I/O I I I I/O I/O I/O I/O I/O I/O Serial data input. 0.5, 1, 2, or 4 kHz frequency output for buzzer sound. External interrupts. The triggering edge for INT0 and INT1 is selectable. Quasi-interrupt with detection of rising or falling edges. External interrupt with a detection of rising and falling edge. Clock output . Timer/counter 0 clock output. Timer/counter 1 clock output. External clock input for timer/counter 0. External clock input for timer/counter 1. 4-Channel comparator input CIN0-CIN2: comparator input only CIN3: comparator input or external reference input DTMF output LCD clock output LCD synchronization clock output. LCD common signal output. Description Share Pin P0.2/K2 P0.3/K3 P1.0, P1.1 P1.2 P1.3 P2.0 P3.0 P3.1 P3.2 P3.3 P7.0/SEG55 P7.1/SEG54 P7.2/SEG53 P7.3/SEG52 - P8.0/SEG51 P8.1/SEG50 - P4.0-P4.3 P5.0-P5.3 - P10.3-P6.0 P0.0-P0.3 P6.0-P6.3 - - -
O I/O I/O O I/O
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
S3C7565/P7565
PRODUCT OVERVIEW
Table 1-2. Supplemental S3C7565 Pin Data Pin Names P0.0-P0.3 P1.0-P1.3 P2.0 P2.1 P2.2 P3.0-P3.1 P3.2-P3.3 P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 P7.0-P7.2 P7.3 P8.0-P8.1 P8.2-P8.3 P9.0-P9.3 P10.0-P10.3 COM0-COM7 SEG0-SEG39 DTMF VDD VSS RESET VLC1 XIN, XOUT XTIN, XTOUT TEST Share Pins SCK/K0, SO/K1, SI/K2, BUZ/K3 INT0, INT1 and INT2, INT4 CLO VLC1 - TCLO0, TCLO1 TCL0, TCL1 COM8-COM11 COM12-COM15 SEG59/K4- SEG56/K7 SEG55/CIN0- SEG53/CIN2 SEG52/CIN3 SEG51-SEG50 SEG49-SEG48 SEG47-SEG44 SEG43-SEG40 - - - - - - - - - - I/O Type I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O - - I - - - I
RESET Value
Circuit Type E-4 A-4 E-4 E-7 E-4 E-2 E-4 H-24 H-25 H-26 H-27 H-28 H-24 H-24 H-24 H-3 H-3 G-7 - - B - - - -
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input High High High impedance - - - - - - -
1-7
PRODUCT OVERVIEW
S3C7565/P7565
PIN CIRCUIT DIAGRAMS
VDD
VDD Pull-Up Resistor In
P-Channel In N-Channel
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD Pull-Up Resistor Pull-Up Resistor Enable In Data
VDD
P-CH Out
Output DIsable Schmitt Trigger
N-CH
Figure 1-4. Pin Circuit Type A-4
Figure 1-6. Pin Circuit Type C
1-8
S3C7565/P7565
PRODUCT OVERVIEW
VDD PNE Pull-up Resistor Pull-up Resistor Enable I/O N-CH
VDD
P-CH Data Output DIsable
Figure 1-7. Pin Circuit Type E-2
VDD PNE Pull-up Resistor Pull-up Resistor Enable I/O N-CH
VDD
P-CH Data Output DIsable
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-4
1-9
PRODUCT OVERVIEW
S3C7565/P7565
VDD PNE Pull-up Resistor Pull-up Resistor Enable I/O N-CH
VDD
P-CH Data Output DIsable
Digital Input VLCEN VLC1
Figure 1-9. Pin Circuit Type E-7
1-10
S3C7565/P7565
PRODUCT OVERVIEW
VLC1
VLC2
VLC3
COM/SEG
VLC4
VLC5
VLC6
Figure 1-10. Pin Circuit Type H-3
1-11
PRODUCT OVERVIEW
S3C7565/P7565
VLC1
VLC2
VLC3
SEG/COM Data Output DIsable
Out
VLC4
VLC5
VSS
Figure 1-11. Pin Circuit Type H-23
1-12
S3C7565/P7565
PRODUCT OVERVIEW
VDD Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD_ON Data Output DIsable Circuit Type H-23 Circuit Type C
I/O
Figure 1-12. Pin Circuit Type H-24
VDD Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD_ON Data Output DIsable Circuit Type H-23 Circuit Type C
I/O
Figure 1-13. Pin Circuit Type H-25
1-13
PRODUCT OVERVIEW
S3C7565/P7565
VDD Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD_ON Data Output DIsable Analog Input SEL Digital In Circuit Type H-23 Circuit Type C P-CH
I/O
Analog In
Figure 1-14. Pin Circuit Type H-26
1-14
S3C7565/P7565
PRODUCT OVERVIEW
VDD Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD OUT EN Data Output DIsable Analog Input SEL Digital In Circuit Type H-23 Circuit Type C P-CH
I/O
External REF SEL
Analog In External REF In
Figure 1-15. Pin Circuit Type H-27
1-15
PRODUCT OVERVIEW
S3C7565/P7565
VDD Pull-up Resistor Pull-up Resistor Enable COM/SEG LCD_ON LCDCK/CLDSY LCDCK/LCDSY Enable Output DIsable Circuit Type C I/O Circuit Type H-23
Figure 1-16. Pin Circuit Type H-28
DTMF Out + Disable
Figure 1-17. Pin Circuit Type G-7
1-16
S3C7565/P7565
ELECTRICAL DATA
16
OVERVIEW
ELECTRICAL DATA
In this section, information on S3C7565 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- A.C. electrical characteristics -- Operating voltage range Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at XIN -- Clock timing measurement at XTIN -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing
16-1
ELECTRICAL DATA
S3C7565/P7565
Table 16-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL Ports 0-10 - One I/O pin active All I/O pins active Output Current Low One I/O pin active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 (Peak value) + 15 (note) Total for ports 0, 2-10 Operating Temperature Storage Temperature TA TSTG - -
Duty .
Units V V V mA
mA
+ 100 (Peak value) + 60 (note) - 40 to + 85 - 65 to + 150
C C
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value x
Table 16-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage Output Low Voltage VOH Conditions All input pins except those specified below for VIH2-VIH3 Ports 0, 1, 2, 6, P3.2, P3.3, and RESET XIN, XOUT, and XTIN All input pins except those specified below for VIL2-VIL3 Ports 0, 1, 2, 6, P3.2, P3.3, and RESET XIN, XOUT, and XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 2-10 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 0, 2-10 VDD - 1.0 - Min 0.7 VDD 0.8 VDD VDD - 0.1 - - Typ - Max VDD VDD VDD 0.3VDD 0.2VDD 0.1 - V V Units V
VOL
-
-
2.0
V
16-2
S3C7565/P7565
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VI = VDD All input pins except those specified below for ILIH2 VI = VDD XIN, XTIN VI = 0 V All input pins except RESET, XIN, XTIN VI = 0 V XIN, XTIN VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 5 V, Port 0-10 VDD = 3 V RL2 VI = 0 V; VDD = 5 V, RESET VDD = 3 V LCD Voltage Dividing Resistor (Note) |VDD-COMi| Voltage Drop (i = 0-15) |VDD-SEGx| Voltage Drop (x = 0-59) VLCX Output Voltage RLCD1 RLCD2 VDC VDD = 2.7 V to 5.5 V - 15 A per common pin VDD = 2.7 V to 5.5 V - 15 A per segment pin VDD = 2.7 V to 5.5 V LCD clock = 0 Hz - - - - 20 3 A - - Min - Typ - Max 3 Units A
ILIH2 Input Low Leakage Current ILIL1
20 -3 A
ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH
ILOL
-
-
-3
A
RLI
25 50 100 200 40 20 -
47 95 220 450 55 28 -
100 200 400 800 70 35 120
k
k
mV
VDS
-
-
120
VLC1 VLC2 VLC3 VLC4 VLC5
VDD-0.2 0.8VDD-0.2 0.6VDD-0.2 0.4VDD-0.2 0.2VDD-0.2
VDD 0.8VDD 0.6VDD 0.4VDD 0.2VDD
VDD + 0.2 0.8VDD +0.2 0.6VDD+0.2 0.4VDD+0.2 0.2VDD+0.2
V
NOTE: RLCD1 is the LCD Voltage dividing resistor when LCON.1 = "0", and RLCD2 when LCON.1 = "1".
16-3
ELECTRICAL DATA
S3C7565/P7565
Table 16-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter
Supply Current (1)
Symbol
IDD1 (DTMF on)
Conditions
Run mode; VDD = 5 V 10 % 3.58 MHz X-tal oscillator, C1 = C2 = 22 pF VDD = 3 V 10 % Run mode; VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% 6.0 MHz 3.58 MHz
Min
-
Typ
3.9
Max
7.0
Units
mA
- -
2.0 4.1 2.7
4.0 8.0 5.0
IDD2 (DTMF off)
IDD3
Idle mode; VDD = 5 V 10 % Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10 %
6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz
-
1.9 1.2 1.2 0.9
4.0 2.3 2.5 1.8
6.0 MHz 3.58 MHz - - -
IDD4 (2) IDD5 (2) IDD6
Run mode; VDD = 3 V 10 % 32 kHz Crystal oscillator Idle mode; VDD = 3 V 10 % 32 kHz Crystal oscillator Stop mode; SCMOD = 0000 XTIN = 0 V VDD = 5 V 10 % VDD = 3 V 10 % Stop mode; VDD = 5 V 10 % VDD = 3 V 10 % SCMOD = 0100
0.5 0.4 17.5 4.8
1.5 1.0 45 15
A A
2.0 0.6 0.2 0.1 - 16.0 1 - 14.0 2
5 3 3 2 - 11.0 3
A
Row Tone level Ratio of Column to Row tone Distortion (Dual tone)
VROW dBCR
RL = 12 K; Temp = - 30 to 60 C VDD = 2 to 5.5 V RL = 12 K; Temp = - 30 to 60 C VDD = 2 to 5.5 V 1 MHz band RL = 12 K; Temp = - 30 to 60 C
VDD = 2 to 5.5 V
dBV
THD
-
-
5
%
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the subsystem clock is used. 3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and output port drive currents.
16-4
S3C7565/P7565
ELECTRICAL DATA
Table 16-3. Main System Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
Parameter Oscillation frequency (1)
Test Condition VDD = 2.7 V to 5.5 V
Min 0.4
Typ -
Max 6.0
Units MHz
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range; VDD = 3.0 V VDD = 2.7 V to 5.5 V
0.4 -
- -
3 4 ms
Crystal Oscillator
XIN
XOUT
Oscillation frequency (1)
0.4
-
6.0
MHz
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) VDD = 3 V VDD = 1.8 V to 5.5 V External Clock
XIN XOUT
0.4 - - 0.4
- - - -
3 10 30 6.0 MHz ms
XIN input frequency (1)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) RC Oscillator
XIN R XOUT
0.4 83.3 -
- - 2
3 1,250 - ns MHz
- R = 25 k, VDD = 5 V
Frequency
R = 40 k, VDD = 3 V
-
1
-
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
16-5
ELECTRICAL DATA
S3C7565/P7565
Table 16-4. Recommended Oscillator Constants (TA = - 40 C to + 85 C) Manufacturer Series Number (1) FCR FCR CCR M5 MC5 MC3 Frequency Range Load Cap (pF) C1 TDK 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
Table 16-5. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTIN XTOUT
Parameter
Test Condition
Min 32
Typ 32.768
Max 35
Units kHz
Oscillation frequency (1) VDD = 1.8 V to 5.5 V
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V
- - 32
1.0 - -
2 10 100
s
External Clock
XTIN XTOUT Open
XTIN input frequency (1) VDD = 1.8 V to 5.5 V
kHz
XTIN input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
16-6
S3C7565/P7565
ELECTRICAL DATA
Table 16-6. Input/output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
Table 16-7. Comparator Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.0 V to 5.5 V, VSS = 0 V) Parameter Input Voltage Range Reference Voltage Range Input Voltage Accuracy Input Leakage Current Symbol - VREF VCIN ICIN, IREF Condition - - - - Min 0 0 - -3 Typ - - - - Max VDD VDD 150 3 Units V V mV A
16-7
ELECTRICAL DATA
S3C7565/P7565
Table 16-8. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time (note) Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0, TCL1 Input Frequency f TI0, f TI1 VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0, TCL1 Input High, Low Width tTIH0, tTIL0 tTIH1, tTIL1 tKCY VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V SCK Cycle Time VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V External SCK source Internal SCK source; Output 0.48 1.8 800 650 3200 3800 - - ns - Min 0.67 1.33 0 - Typ - Max 64 64 1.5 1 - s MHz Units s
16-8
S3C7565/P7565
ELECTRICAL DATA
Table 16-8. A.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter SCK High, Low Width Symbol tKH, tKL Conditions VDD = 2.7 V to 5.5 V External SCK source Internal SCK source VDD = 1.8 V to 5.5 V Internal SCK source SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 1.8 V to 5.5 V; Input VDD = 1.8 V to 5.5 V; Output SI Hold Time to SCK High tKSI VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 1.8 V to 5.5 V; Input VDD = 1.8 V to 5.5 V; Output Output Delay for SCK to SO tKSO VDD = 2.7 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output VDD = 1.8 V to 5.5 V; Input VDD = 2.7 V to 5.5 V; Output Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT0-INT2, INT4, KS0-KS7 Input 10 10 - - Min 325 TkCY/ 2-50 1600 tKCY/ 2-150 100 150 150 500 400 400 600 500 - - 300 250 1000 1000 - - s s ns - - ns - - ns Typ - Max - Units ns
External SCK source
NOTE: Unless specified the otherwise, Instruction Cycle Time condition values assume a main system clock (fx) source.
16-9
ELECTRICAL DATA
S3C7565/P7565
CPU Clock 1.5MHz
Main Os. Freq. (Divided by 4) 6MHz
1.05MHz 0.75kHz
4.2MHz 3MHz
15.625kHz 1 2 1.8 3 2.7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64) 4 5 6 7
Figure 16-1. Standard Operating Voltage Range
Table 16-9. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 5.5 10 - - -
Unit V A s ms
NOTES: 1. During the oscillator stabilization wait time, all the CPU operations must be stopped to avoid instability that can occur during the oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay an execution of CPU instructions during the wait time.
16-10
S3C7565/P7565
ELECTRICAL DATA
TIMING WAVEFORMS
Internal Reset Operation Stop Mode Data Retention Mode Idle Mode Operating Mode
~ ~ ~ ~
VDD
VDDDR Execution of STOP Instruction RESET tWAIT tSREL
Figure 16-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~ ~ ~ ~
Stop Mode Data Retention Mode
Normal Operating Mode
VDD
VDDDR Execution of STOP Instrction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 16-3. Stop Mode Release Timing When Initiated by Interrupt Request
16-11
ELECTRICAL DATA
S3C7565/P7565
0.8 VDD Measurement Points 0.2 VDD
0.8 VDD
0.2 VDD
Figure 16-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx tXL tXH
XIN
VDD - 0.1 V 0.1 V
Figure 16-5. Clock Timing Measurement at XIN
1/fxt tXTL tXTH
XTIN
VDD - 0.1 V 0.1 V
Figure 16-6. Clock Timing Measurement at XTIN
16-12
S3C7565/P7565
ELECTRICAL DATA
1/fTI tTIL tTIH
TCL0
0.8 VDD 0.2 VDD
Figure 16-7. TCL Timing
tRSL
RESET 0.2 VDD
Figure 16-8. Input Timing for RESET Signal
16-13
ELECTRICAL DATA
S3C7565/P7565
tINTL
tINTH
INT0, 1, 2, 4 K0 to K7
0.8 VDD 0.2 VDD
Figure 16-9. Input Timing for External Interrupts and Quasi-Interrupts
tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO tKH
SO
Output Data
Figure 16-10. Serial Data Transfer Timing
16-14
S3C7565/P7565
MECHANICAL DATA
17
-- Pad diagram
MECHANICAL DATA
This section contains the following information about the device package: -- Package dimensions in millimeters -- Pad/pin coordinate data table
23.90 0.3
0-8
O
20.00 0.2
0.15
+0.10 _0.05
17.00 0.3
14.00 0.2
100-QFP-1420C
0.10 MAX
#1
0.30 0.1 0.10 MAX
0.65
(0.58)
(0.83)
0.05 MIN 2.65 0.10 3.00 MAX
NOTE: Dimensions are in millimeters.
0.80 0.20
Figure 17-1. 100-QFP Package Dimensions
0.80 0.20
#100
17-1
MECHANICAL DATA
S3C7565/P7565
NOTES
17-2
S3C7565/P7565
S3P7565 OTP
18
OVERVIEW
S3P7565 OTP
The S3P7565 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7565 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P7565 is fully compatible with the S3C7565, both in function and in pin configuration. Because of its simple programming requirements, the S3P7565 is ideal for use as an evaluation chip for the S3C7565.
18-1
S3P7565 OTP
S3C7565/P7565
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 DTMF P0.0/SCK/K0 P0.1/SO/K1 SDAT/P0.2/SI/K2 SCLK/P0.3/BUZ/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/CLO P2.1/VLC1 P2.2 P3.0/TCLO0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P10.3/SEG40 P10.2/SEG41 P10.1/SEG42 P10.0/SEG43 P9.3/SEG44 P9.2/SEG45 P9.1/SEG46 P9.0/SEG47 P8.3/SEG48 P8.2/SEG49 P8.1/SEG50/LCDSY P8.0/SEG51/LCDCK P7.3/SEG52/CIN3 P7.2/SEG53/CIN2 P7.1/SEG54/CIN1 P7.0/SEG55/CIN0 P6.3/SEG56/K7 P6.2/SEG57/K6 P6.1/SEG58/K5
Figure 18-1. S3P7565 Pin Assignments (100-QFP Package)
S3C7565 (100-QFP-1420C)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P6.0/SEG59/K4 P5.3/COM15 P5.2/COM14 P5.1/COM13 P5.0/COM12 P4.3/COM11 P4.2/COM10 P4.1/COM9 P4.0/COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 P3.3/TCL1 P3.2/TCL0 P3.1/TCLO1
18-2
S3C7565/P7565
S3P7565 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.2 Pin Name SDAT Pin No. 13 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/pushpull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. When OTP is operating, hold GND. (Option) Chip initialization Logic power supply pin. VDD should be tied to + 5 V during programming.
P0.3 TEST
SCLK VPP (TEST)
14 19
I/O I
RESET VDD/VSS
RESET VDD/VSS
22 15/16
I I
Table 18-2. Comparison of S3P7565 and S3C7565 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P7565 16-Kbyte EPROM 1.8 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5V 100 QFP User Program 1 time 100 QFP Programmed at the factory S3C7565 16-Kbyte mask ROM 1.8 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P7565, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 18-3 below. Table 18-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection R/W Mode
NOTE: "0" means Low level; "1" means High level.
18-3
S3P7565 OTP
S3C7565/P7565
Table 18-4. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL Ports 0-10 - One I/O pin active All I/O pins active Output Current Low One I/O pin active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 35 + 30 (Peak value) + 15 (note) Total for ports 0, 2-10 Operating Temperature Storage Temperature TA TSTG - - + 100 (Peak value) + 60 (note) - 40 to + 85 - 65 to + 150
Duty . C C
Units V V V mA
mA
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value x
18-4
S3C7565/P7565
S3P7565 OTP
Table 18-5. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Output High Voltage Output Low Voltage VOH Conditions All input pins except those specified below for VIH2-VIH3 Ports 0, 1, 2, 6, P3.2, P3.3, and RESET XIN, XOUT, and XTIN All input pins except those specified below for VIL2-VIL3 Ports 0, 1, 2, 6, P3.2, P3.3, and RESET XIN, XOUT, and XTIN VDD = 4.5 V to 5.5 V IOH = - 1 mA Ports 0, 2-10 VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 0, 2-10 Input High Leakage Current ILIH1 VI = VDD All input pins except those specified below for ILIH2 VI = VDD XIN, XTIN All input pins except RESET, XIN, XTIN VI = 0 V XIN, XTIN VO = VDD All output pins VO = 0 V All output pins - - - 20 3 A VI = 0 V - - - - 3 A VDD - 1.0 - Min 0.7 VDD 0.8 VDD VDD - 0.1 - - Typ - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - V V Units V
VOL
-
-
2.0
V
ILIH2 Input Low Leakage Current ILIL1
20 -3 A
ILIL2 Output High Leakage Current Output Low Leakage Current ILOH
ILOL
-
-
-3
A
18-5
S3P7565 OTP
S3C7565/P7565
Table 18-5. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Pull-up Resistor Symbol RLI Conditions VI = 0 V; VDD = 5 V, Port 0-10 VDD = 3 V RL2 VI = 0 V; VDD = 5 V, RESET VDD = 3 V LCD Voltage Dividing Resistor (note) |VDD-COMi| Voltage Drop (i = 0-15) |VDD-SEGx| Voltage Drop (x = 0-59) VLCX Output Voltage RLCD1 RLCD2 VDC VDD = 2.7 V to 5.5 V - 15 A per common pin VDD = 2.7 V to 5.5 V - 15 A per segment pin VDD = 2.7 V to 5.5 V LCD clock = 0 Hz - Min 25 50 100 200 40 20 - Typ 47 95 220 450 55 28 - Max 100 200 400 800 70 35 120 mV k Units k
VDS
-
-
120
VLC1 VLC2 VLC3 VLC4 VLC5
VDD-0.2 0.8VDD-0.2 0.6VDD-0.2 0.4VDD-0.2 0.2VDD-0.2
VDD 0.8VDD 0.6VDD 0.4VDD 0.2VDD
VDD+0.2 0.8VDD+0.2 0.6VDD+0.2 0.4VDD+0.2 0.2VDD+0.2
V
NOTE: RLCD1 is the LCD Voltage dividing resistor when LCON.1 = "0", and RLCD2 is the one when LCON.1 = "1".
18-6
S3C7565/P7565
S3P7565 OTP
Table 18-5. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 Conditions Min - Typ 3.9 Max 7.0 Units mA Run mode; VDD = 5 V 10 % (DTMF on) 3.58 MHz X-tal oscillator, C1 = C2 = 22 pF VDD = 3 V 10% IDD2 Run mode; (DTMF off) VDD = 5 V 10 % Crystal oscillator C1 = C2 = 22 pF
VDD = 3 V 10 %
- 6.0 MHz 3.58 MHz
2.0 4.1 2.7
4.0 8.0 5.0
6.0 MHz 3.58 MHz 6.0 MHz 3.58 MHz -
1.9 1.2 1.2 0.9
4.0 2.3 2.5 1.8
IDD3
Idle mode; VDD = 5 V 10 % Crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10 %
6.0 MHz 3.58 MHz - - -
0.5 0.4 17.5 y 2.0 0.6 0.2 0.1 - 16.0 1 - - 14.0 2 -
1.5 1.0 45 15 5 3 3 2 - 11.0 3 5 % dBV A A A
IDD4 (2) IDD5 (2) IDD6
Run mode; VDD = 3 V 10 % 32 kHz Crystal oscillator Idle mode; VDD = 3 V 10 % 32 kHz Crystal oscillator Stop mode; VDD = 5 V 10 % VDD = 3 V 10 % Stop mode; VDD = 5 V 10 % VDD = 3 V 10 % SCMOD = 0000 XTIN = 0 V SCMOD = 0100
Row Tone Level Ratio of Column to Row tone Distortion (Dual tone)
VROW dBCR THD
VDD = 2 to 5.5 V RL = 12 K; Temp = - 30 to 60 C VDD = 2 to 5.5 V RL = 12 K; Temp = - 30 to 60 C VDD = 2 to 5.5 V 1 MHz band RL = 12 K; Temp = - 30 to 60 C
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the subsystem clock is used. 3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and output port drive currents.
18-7
S3P7565 OTP
S3C7565/P7565
Table 18-6. Main System Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration
XIN XOUT
Parameter Oscillation frequency (1)
Test Condition VDD = 2.7 V to 5.5 V
Min 0.4
Typ -
Max 6.0
Unit s MHz
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) Stabilization occurs when VDD is equal to the minimum oscillator voltage range; VDD = 3.0 V VDD = 2.7 V to 5.5 V
0.4 -
- -
3.0 4 ms
Crystal Oscillator
XIN
XOUT
Oscillation frequency (1)
0.4
-
6.0
MHz
C1
C2
VDD = 1.8 V to 5.5 V Stabilization time (2) VDD = 3 V VDD = 1.8 V to 5.5 V External Clock
XIN XOUT
0.4 - - 0.4
- - - -
3.0 10 30 6.0 MHz ms
XIN input frequency (1)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) RC Oscillator
XIN R XOUT
0.4 83.3 -
- - 2
3.0 1,250 - ns MHz
- R = 25 k, VDD = 5 V
Frequency
R = 40 k, VDD = 3 V
-
1
-
NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
18-8
S3C7565/P7565
S3P7565 OTP
Table 18-7. Subsystem Clock Oscillator Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Oscillator Clock Configuration
XTIN XTOUT
Parameter Oscillation frequency (1)
Test Condition VDD = 1.8 V to 5.5 V
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V
- - 32
1.0 - -
2 10 100
s
External Clock
XTIN XTOUT Open
XTIN input frequency (1)
VDD = 1.8 V to 5.5 V
kHz
XTIN input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 18-8. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
18-9
S3P7565 OTP
S3C7565/P7565
CPU Clock 1.5MHz
Main Os. Freq. (Divided by 4) 6MHz
1.05MHz 0.75kHz
4.2MHz 3MHz
15.625kHz 1 2 1.8 3 2.7 Supply Voltage (V) CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64) 4 5 6 7
Figure 18-2. Standard Operating Voltage Range
18-10

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